SafeSU: an Extended Statistics Unit for Multicore Timing Interference

May 1, 2021·
G. Cabo
,
F. Bas
,
R. Lorenzo
,
D. Trilla
Dr. Sergi Alcaide Portet
Dr. Sergi Alcaide Portet
,
M. Moreto
,
C. Hernandez
,
J. Abella
· 0 min read
Type
Publication
2021 IEEE European Test Symposium (ETS)
publications
Multicore & MPSoC Timing Interference & Validation
Authors
G. Cabo
Authors
F. Bas
Authors
R. Lorenzo
Authors
D. Trilla
Dr. Sergi Alcaide Portet
Authors
Dr. Sergi Alcaide Portet (he/him)
Postdoc | Research Engineer
Sergi Alcaide is a PostDoc in the HADES group, within the HPES Lab @ BSC (Barcelona Supercomputing Center)
Authors
M. Moreto
Authors
C. Hernandez
Authors
J. Abella