De-RISC

Tue, 01 Oct 2019 00:00:00 +0000

🌐 Project Webpage: | 🇪🇺 CORDIS Factsheet:

De-RISC (Dependable Real-time Infrastructure for Safety-critical Computer) is a European Horizon 2020 Fast Track to Innovation project (Grant Agreement EIC-FTI 869945) that developed a complete space-grade hardware and software platform based on open-source RISC-V architecture.

📅 Project Timeline & Factsheet

Start Date: October 1, 2019
End Date: September 30, 2022
Duration: 36 Months
Funding Scheme: Horizon 2020 (Fast Track to Innovation - GA EIC-FTI 869945)
Grant Agreement ID: 869945
Overall Budget: €3,444,625 (€2,617,937.50 EU Contribution)

🎯 Objectives & Scope

The primary objective of De-RISC was to achieve European technological sovereignty in space computing by delivering a fully European, dependable hardware-software platform for satellite payloads and launcher flight computers, eliminating reliance on non-European proprietary components.

💡 Key Research Innovations

Quad-Core NOEL-V RISC-V Processor SoC: Developed and space-qualified a fault-tolerant quad-core RISC-V multi-core processor SoC.
SafeSU (Safe Statistics Unit): Designed and integrated an on-chip hardware performance counter module to capture multi-core contention and establish tight worst-case execution time (WCET) bounds.
Space Virtualization with Xtratum: Seamlessly integrated space-qualified hypervisor virtualization to host mixed-criticality software partitions with strict spatial and temporal isolation.

🏛️ BSC Key Role & Research Deliverables

As a core research partner in De-RISC, Barcelona Supercomputing Center (BSC) led the microarchitectural safety and timing analysis efforts:

SafeSU Hardware Unit: Conceptualized, designed, and implemented the SafeSU hardware statistics unit for monitoring interconnect contention on NOEL-V platforms.
Multi-Core Interference Characterization: Formulated execution models and timing analysis techniques for evaluating shared-resource contention under space workloads.
Lockstep & Isolation Architectures: Researched lockstep NOEL-V core designs (SafeLS) and hardware execution isolation mechanisms (SafeX).

📚 Associated Publications

G. Cabo, F. Bas, R. Lorenzo, D. Trilla, S. Alcaide, M. Moreto, C. Hernandez, J. Abella — IEEE ETS 2021 ( )
S. Alcaide, G. Cabo, F. Bas, C. Hernandez, J. Abella — IEEE Micro 2023 ( )

🏛️ Consortium Partners

(Partners are listed in no particular order)

The De-RISC consortium brought together leading European space industry, hypervisor, and supercomputing pioneers:

🇪🇸 (Spain, Coordinator)
🇪🇸 (Spain)
🇫🇷 (France)
🇸🇪 (Sweden)