Safety-Critical Systems |

Introduction to Post Quantum Cryptography for Resource Constrained Systems

Thu, 01 Jan 2026 00:00:00 +0000

SMARTY

Mon, 01 Jan 2024 00:00:00 +0000

SMARTY is an active European project funded under the Chips Joint Undertaking (Chips JU) aimed at building smart, dependable, and high-performance computing architectures for next-generation safety-critical applications.

🎯 Objectives & Scope

Modern critical systems (autonomous driving, avionics, industrial robotics) require massive compute power alongside strict functional safety (ISO 26262 ASIL-D, DO-254). SMARTY bridges this gap through intelligent hardware/software co-design.

💡 Key Research Focus

Hardware-Enforced Isolation: Advanced hardware partitioning mechanisms ensuring zero-interference between critical real-time tasks and AI acceleration workloads.
RISC-V Safety Extensions: Extending open-source RISC-V cores with custom safety-monitoring hardware units.
Smart Contention Control: Machine-learning-assisted dynamic bandwidth allocation to mitigate interconnect contention in complex SoCs.

🏛️ Target Domains

Autonomous Automotive Systems
Next-Gen Avionics & Aerospace Flight Computers
Smart Industrial Automation

AR2SEC (Misiones)

Sun, 01 Jan 2023 00:00:00 +0000

AR2SEC is a Spanish national strategic initiative funded under the CDTI Misiones program, dedicated to advancing reliable, resilient hardware and software architectures for Spanish industry.

🎯 Objectives & Scope

AR2SEC focused on providing verifiable safety, diversity, and timing bounds for multi-core processors deployed in high-consequence industrial and automotive systems.

💡 Key Research Innovations

DIMP (Diversity Metric): Created circuit-path diversity metrics to quantify execution path independence in redundant execution units.
SafeDE (Diversity Enforcement): Implemented lightweight hardware modules enforcing microarchitectural execution diversity on non-lockstepped cores.
SafeTI (Traffic Injector): Built hardware traffic injection units for black-box IP characterization and SoC timing interference analysis under worst-case contention scenarios.

🏛️ Funding & Scope

Funding Body: CDTI (Centro para el Desarrollo Tecnológico y la Innovación) — Programa Misiones
Scope: Spanish National Research & Industrial Leadership

Envisioning a Safety Island to Enable HPC Devices in Safety-Critical Domains

Sun, 01 Jan 2023 00:00:00 +0000

Hardware/software solutions to enable the use of high-performance processors in the most stringent safety-critical systems

Sun, 01 Jan 2023 00:00:00 +0000

End-to-End QoS for the Open Source Safety-Relevant RISC-V SELENE Platform

Sat, 01 Jan 2022 00:00:00 +0000

SafeDX: Standalone Modules Providing Diverse Redundancy for~Safety-Critical Applications

Sat, 01 Jan 2022 00:00:00 +0000

SafeSoftDR: A Library to Enable Software-Based Diverse Redundancy for Safety-Critical Tasks

Sat, 01 Jan 2022 00:00:00 +0000

SafeX: Open Source Hardware and Software Components for Safety-Critical Systems

Sat, 01 Jan 2022 00:00:00 +0000

Software-only based Diverse Redundancy for ASIL-D Automotive Applications on Embedded HPC Platforms

Wed, 01 Jan 2020 00:00:00 +0000

High-Integrity GPU Designs for Critical Real-Time Automotive Systems

Fri, 01 Mar 2019 00:00:00 +0000