RISC-V |

Application of Tiny RISC-V: Invited paper

Thu, 01 Jan 2026 00:00:00 +0000

Hardware-Enforced Throughput Quotas for Mitigating Accelerator Interference in Mixed-Criticality SoCs

Thu, 01 Jan 2026 00:00:00 +0000

Introduction to Post Quantum Cryptography for Resource Constrained Systems

Thu, 01 Jan 2026 00:00:00 +0000

ISOLDE

Mon, 01 Jan 2024 00:00:00 +0000

ISOLDE (High Performance, Safe, Secure, Open-Source Leveraged RISC-V Domain-Specific Ecosystems) is a major European initiative under the Chips Joint Undertaking (Chips JU) uniting over 40 European industrial and academic partners.

🎯 Objectives & Scope

ISOLDE delivers high-performance, open-source European RISC-V processor IP cores and specialized domain accelerators for automotive, space, and industrial IoT sectors.

💡 Key Research Focus

Industrial RISC-V IP Cores: Maturing open-source RISC-V processing cores to industrial readiness levels (TRL 7/8).
Domain-Specific Accelerators: Developing customizable hardware accelerators for neural networks, signal processing, and cryptography.
Safety & Security Standards: Validating RISC-V architectures against ISO 26262, IEC 61508, and Common Criteria security standards.

🏛️ Consortium

40+ European Industrial & Academic Partners
Funding: Chips Joint Undertaking (Chips JU) & National Funding Authorities

SMARTY

Mon, 01 Jan 2024 00:00:00 +0000

SMARTY is an active European project funded under the Chips Joint Undertaking (Chips JU) aimed at building smart, dependable, and high-performance computing architectures for next-generation safety-critical applications.

🎯 Objectives & Scope

Modern critical systems (autonomous driving, avionics, industrial robotics) require massive compute power alongside strict functional safety (ISO 26262 ASIL-D, DO-254). SMARTY bridges this gap through intelligent hardware/software co-design.

💡 Key Research Focus

Hardware-Enforced Isolation: Advanced hardware partitioning mechanisms ensuring zero-interference between critical real-time tasks and AI acceleration workloads.
RISC-V Safety Extensions: Extending open-source RISC-V cores with custom safety-monitoring hardware units.
Smart Contention Control: Machine-learning-assisted dynamic bandwidth allocation to mitigate interconnect contention in complex SoCs.

🏛️ Target Domains

Autonomous Automotive Systems
Next-Gen Avionics & Aerospace Flight Computers
Smart Industrial Automation

Enhancing Safety with RISC-V-based SPIDER Autonomous Robot: A Use-Case from the ECSEL FRACTAL Project

Thu, 01 Jun 2023 00:00:00 +0000

SafeLS: An Open Source Implementation of a Lockstep NOEL-V RISC-V Core

Sun, 01 Jan 2023 00:00:00 +0000

SafeLS: Toward Building a Lockstep NOEL-V Core

Sun, 01 Jan 2023 00:00:00 +0000

De-RISC: A Complete RISC-V Based Space-Grade Platform

Sat, 01 Jan 2022 00:00:00 +0000

End-to-End QoS for the Open Source Safety-Relevant RISC-V SELENE Platform

Sat, 01 Jan 2022 00:00:00 +0000

Security, Reliability and Test Aspects of the RISC-V Ecosystem

Sat, 01 May 2021 00:00:00 +0000

SELENE

Wed, 01 Jan 2020 00:00:00 +0000

🌐 GitLab Repository: | 🇪🇺 CORDIS Factsheet:

SELENE (Self-monitored Dependable platform for High-Performance Safety-Critical Systems) was a European Horizon 2020 project (Grant Agreement 871467) that designed a safety-relevant, open-source high-performance RISC-V system-on-chip.

📅 Project Timeline & Factsheet

Start Date: December 1, 2019
End Date: November 30, 2022
Duration: 36 Months
Funding Scheme: Horizon 2020 (Research and Innovation Action - H2020 GA 871467)
Grant Agreement ID: 871467
Overall Budget: €4,996,526.25 (€4,996,523 EU Contribution)

🎯 Objectives & Scope

SELENE addressed the challenge of executing mixed-criticality workloads (combining safety-critical flight and automotive control tasks with high-throughput payload processing) on shared multi-core RISC-V hardware with guaranteed Quality of Service (QoS).

💡 Key Research Innovations

End-to-End Interconnect QoS: Implemented hardware-enforced throughput quotas and priority arbitration across shared buses and memory controllers.
Self-Monitoring & Fault Tolerance: Integrated dynamic health monitoring and lockstep NOEL-V execution modes for dynamic fault isolation.
DAVOS Verification Toolkit: Developed automated fault injection and safety validation tools for RISC-V SoCs.

🏛️ BSC Key Role & Research Deliverables

As a primary research leader in SELENE, Barcelona Supercomputing Center (BSC) drove the interconnect QoS and safety validation research:

Interconnect Throughput Quotas: Designed hardware bandwidth allocation and throttling mechanisms ensuring zero-interference for critical tasks.
DAVOS Fault Injection Framework: Created DAVOS, an open-source automated fault injection framework for safety-critical hardware validation.
Traffic Injection Units: Developed hardware traffic injectors (SafeTI) to test multi-core interference under worst-case contention scenarios.

📚 Associated Publications

S. Alcaide, G. Cabo, C. Hernandez, J. Abella — DATE 2022 ( )
M. Sala, S. Alcaide, F. Bas, G. Cabo, R. Lorenzo, C. Hernandez, J. Abella — IEEE IOLTS 2021 ( )
S. Alcaide, M. Sala, F. Bas, G. Cabo, R. Lorenzo, C. Hernandez, J. Abella — IEEE IOLTS 2021 ( )
J. Abella, S. Alcaide, et al. — IEEE ETS 2021 ( )
S. Alcaide, L. Kosmidis, C. Hernandez, J. Abella — IEEE TETC 2022 ( )
F. Fuentes, R. Casanova, S. Alcaide, J. Abella — arXiv / IEEE 2023 ( )

🏛️ Consortium Partners

(Partners are listed in no particular order)

The SELENE consortium brought together 11 leading European aerospace, automotive, railway, and research institutions:

🇪🇸 (Spain, Coordinator)
🇪🇸 (Spain)
🇪🇸 (Spain)
🇪🇸 (Spain)
🇸🇪 (Sweden)
🇫🇷 (France)
🇩🇪 (Germany)
🇩🇪 (Germany)
🇦🇹 (Austria)
🇦🇹 (Austria)
🇦🇹 (Austria)

De-RISC

Tue, 01 Oct 2019 00:00:00 +0000

🌐 Project Webpage: | 🇪🇺 CORDIS Factsheet:

De-RISC (Dependable Real-time Infrastructure for Safety-critical Computer) is a European Horizon 2020 Fast Track to Innovation project (Grant Agreement EIC-FTI 869945) that developed a complete space-grade hardware and software platform based on open-source RISC-V architecture.

📅 Project Timeline & Factsheet

Start Date: October 1, 2019
End Date: September 30, 2022
Duration: 36 Months
Funding Scheme: Horizon 2020 (Fast Track to Innovation - GA EIC-FTI 869945)
Grant Agreement ID: 869945
Overall Budget: €3,444,625 (€2,617,937.50 EU Contribution)

🎯 Objectives & Scope

The primary objective of De-RISC was to achieve European technological sovereignty in space computing by delivering a fully European, dependable hardware-software platform for satellite payloads and launcher flight computers, eliminating reliance on non-European proprietary components.

💡 Key Research Innovations

Quad-Core NOEL-V RISC-V Processor SoC: Developed and space-qualified a fault-tolerant quad-core RISC-V multi-core processor SoC.
SafeSU (Safe Statistics Unit): Designed and integrated an on-chip hardware performance counter module to capture multi-core contention and establish tight worst-case execution time (WCET) bounds.
Space Virtualization with Xtratum: Seamlessly integrated space-qualified hypervisor virtualization to host mixed-criticality software partitions with strict spatial and temporal isolation.

🏛️ BSC Key Role & Research Deliverables

As a core research partner in De-RISC, Barcelona Supercomputing Center (BSC) led the microarchitectural safety and timing analysis efforts:

SafeSU Hardware Unit: Conceptualized, designed, and implemented the SafeSU hardware statistics unit for monitoring interconnect contention on NOEL-V platforms.
Multi-Core Interference Characterization: Formulated execution models and timing analysis techniques for evaluating shared-resource contention under space workloads.
Lockstep & Isolation Architectures: Researched lockstep NOEL-V core designs (SafeLS) and hardware execution isolation mechanisms (SafeX).

📚 Associated Publications

G. Cabo, F. Bas, R. Lorenzo, D. Trilla, S. Alcaide, M. Moreto, C. Hernandez, J. Abella — IEEE ETS 2021 ( )
S. Alcaide, G. Cabo, F. Bas, C. Hernandez, J. Abella — IEEE Micro 2023 ( )

🏛️ Consortium Partners

(Partners are listed in no particular order)

The De-RISC consortium brought together leading European space industry, hypervisor, and supercomputing pioneers:

🇪🇸 (Spain, Coordinator)
🇪🇸 (Spain)
🇫🇷 (France)
🇸🇪 (Sweden)