RISC-V

Introduction to Post Quantum Cryptography for Resource Constrained Systems

Hardware-Enforced Throughput Quotas for Mitigating Accelerator Interference in Mixed-Criticality SoCs

As open-source Systems-on-Chip (SoCs) scale in complexity, mitigating timing interference across shared resources remains a critical challenge for mixed-criticality applications. …

Application of Tiny RISC-V: Invited paper

Specialized tiny RISC-V cores, typically coupled with scratchpad memories, offer opportunities to manage application-specific units efficiently and autonomously. In general, safety …

SMARTY

Smart and Dependable Architecture for Next-Generation Safety-Critical Systems (Chips JU).

ISOLDE

High-Performance Open-Source RISC-V Processors & Domain-Specific Accelerators for Critical Applications (Chips JU).

Enhancing Safety with RISC-V-based SPIDER Autonomous Robot: A Use-Case from the ECSEL FRACTAL Project

The SPIDER use case of the ECSEL FRACTAL project demonstrates the safety capabilities developed in the project on a RISC-V platform. The use case demonstrates the integration of a …

SafeLS: Toward Building a Lockstep NOEL-V Core

SafeLS: An Open Source Implementation of a Lockstep NOEL-V RISC-V Core

End-to-End QoS for the Open Source Safety-Relevant RISC-V SELENE Platform

De-RISC: A Complete RISC-V Based Space-Grade Platform

Security, Reliability and Test Aspects of the RISC-V Ecosystem

SELENE

Self-Monitoring and Self-Healing Open-Source High-Performance RISC-V Platform (Horizon 2020).

De-RISC

Dependable Real-Time Infrastructure for Safety-Critical Space Applications (Horizon 2020).