Ongoing |

ISOLDE

Mon, 01 Jan 2024 00:00:00 +0000

ISOLDE (High Performance, Safe, Secure, Open-Source Leveraged RISC-V Domain-Specific Ecosystems) is a major European initiative under the Chips Joint Undertaking (Chips JU) uniting over 40 European industrial and academic partners.

🎯 Objectives & Scope

ISOLDE delivers high-performance, open-source European RISC-V processor IP cores and specialized domain accelerators for automotive, space, and industrial IoT sectors.

💡 Key Research Focus

Industrial RISC-V IP Cores: Maturing open-source RISC-V processing cores to industrial readiness levels (TRL 7/8).
Domain-Specific Accelerators: Developing customizable hardware accelerators for neural networks, signal processing, and cryptography.
Safety & Security Standards: Validating RISC-V architectures against ISO 26262, IEC 61508, and Common Criteria security standards.

🏛️ Consortium

40+ European Industrial & Academic Partners
Funding: Chips Joint Undertaking (Chips JU) & National Funding Authorities

RIGOLETTO

Mon, 01 Jan 2024 00:00:00 +0000

RIGOLETTO is an ongoing European research project funded under the Chips Joint Undertaking (Chips JU) researching resilient, high-throughput computing architectures for critical real-time MPSoCs.

🎯 Objectives & Scope

RIGOLETTO addresses the challenge of running complex real-time applications on modern multi-core and heterogeneous SoCs while maintaining strict timing predictability and high operational resilience.

💡 Key Research Focus

Predictable MPSoC Interconnects: Designing memory controllers and bus fabrics that guarantee worst-case execution time (WCET) bounds.
Dynamic Hardware Resilience: Implementing runtime fault detection and automatic reconfiguration to recover from transient soft errors.
Heterogeneous Acceleration: Enabling safe integration of AI accelerators into mission-critical control loops.

🏛️ Funding & Scope

Funding: Chips Joint Undertaking (Chips JU)
Focus: Real-Time Dependable Computing & Hardware Resilience

SMARTY

Mon, 01 Jan 2024 00:00:00 +0000

SMARTY is an active European project funded under the Chips Joint Undertaking (Chips JU) aimed at building smart, dependable, and high-performance computing architectures for next-generation safety-critical applications.

🎯 Objectives & Scope

Modern critical systems (autonomous driving, avionics, industrial robotics) require massive compute power alongside strict functional safety (ISO 26262 ASIL-D, DO-254). SMARTY bridges this gap through intelligent hardware/software co-design.

💡 Key Research Focus

Hardware-Enforced Isolation: Advanced hardware partitioning mechanisms ensuring zero-interference between critical real-time tasks and AI acceleration workloads.
RISC-V Safety Extensions: Extending open-source RISC-V cores with custom safety-monitoring hardware units.
Smart Contention Control: Machine-learning-assisted dynamic bandwidth allocation to mitigate interconnect contention in complex SoCs.

🏛️ Target Domains

Autonomous Automotive Systems
Next-Gen Avionics & Aerospace Flight Computers
Smart Industrial Automation