On-chip Traffic Injection to Counteract Timing Side-Channel Attacks
f.-fuentes
SMARTY
Smart and Dependable Architecture for Next-Generation Safety-Critical Systems (Chips JU).
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1 min read
RIGOLETTO
Resilient and High-Performance Architecture for Critical Real-Time MPSoCs (Chips JU).
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1 min read
Unboxing the Sand: on Deploying Safety Measures in the Programmable Logic of COTS MPSoCs
SELENE
Self-Monitoring and Self-Healing Open-Source High-Performance RISC-V Platform (Horizon 2020).
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2 min read