NimbleAI

Thu, 01 Dec 2022 00:00:00 +0000

🌐 Project Webpage: | 🇪🇺 CORDIS Factsheet:

NimbleAI (Ultra-energy efficient and secure neuromorphic sensing and processing at the endpoint) is a Horizon Europe research project (Grant Agreement ID 101070679) funded under the HORIZON-CL4-2021-DIGITAL-EMERGING-01 programme.

📅 Project Timeline & Factsheet

Start Date: October 1, 2022
End Date: March 31, 2026
Duration: 42 Months
Funding Scheme: Horizon Europe (Research and Innovation Action - HORIZON-RIA)
Grant Agreement ID: 101070679
Overall Budget: €6,000,000+ (EU Contribution)

🎯 Objectives & Scope

Traditional visual computing pipelines (cameras connected to separate CPU/GPUs) are highly inefficient, wasting substantial energy transmitting redundant video frames. NimbleAI developed an energy-efficient sensing-processing system operating on event-driven, bio-inspired principles.

💡 Key Research Innovations

Event-Based Sensing: Integrated dynamic event vision sensors that process visual changes at pixel level, eliminating redundant frame capture.
3D Neuromorphic Integration: Stacked sensing layers directly above event-driven in-memory neural processing arrays.
Adaptive Edge AI: Enabled dynamic trade-offs between energy consumption, latency, and inference accuracy for autonomous robotics and IoT nodes.

🏛️ BSC Key Role & Research Deliverables

As a core partner in NimbleAI, Barcelona Supercomputing Center (BSC) led critical research thrusts in neuromorphic hardware architecture and edge AI dependability:

Neuromorphic Execution Trade-Offs: Co-designed the architectural framework balancing bio-inspired event-driven vision processing with 3D stacked in-memory neural acceleration.
Predictability & Dependability: Developed safety and execution models to guarantee bounded response times for edge AI inferences.
Flagship Publication: Led and co-authored the flagship project paper at Design, Automation and Test in Europe (DATE 2023): “NimbleAI: Towards Neuromorphic Sensing-Processing 3D-integrated Chips”.

📚 Associated Publications

X. Iturbe, N. Abderrahmane, J. Abella, S. Alcaide, et al. — DATE 2023 ( )

🏛️ Consortium Partners

(Partners are listed in no particular order)

The NimbleAI consortium brings together 19 leading European research centers, universities, semiconductor companies, and industrial leaders extracted directly from the official project website ( ):

🇪🇸 (Spain, Coordinator)
🇪🇸 (Spain)
🇪🇸 (Spain)
🇪🇸 (Spain)
🇪🇸 (Spain)
🇬🇧 (United Kingdom)
🇬🇧 (United Kingdom)
🇫🇷 (France)
🇫🇷 (France)
🇧🇪 (Belgium)
🇦🇹 (Austria)
🇦🇹 (Austria)
🇦🇹 (Austria)
🇳🇱 (Netherlands)
🇳🇱 (Netherlands)
🇩🇪 (Germany / Czech Republic)
🇩🇪 (Germany)
🇮🇹 (Italy)
🇮🇹 (Italy)
🇺🇸 (United States / Austria)

💼 Industry Advisory Board & Partners

🇪🇺
🇳🇱
🇺🇸
🇺🇸
🇫🇷
🇺🇸

De-RISC

Tue, 01 Oct 2019 00:00:00 +0000

🌐 Project Webpage: | 🇪🇺 CORDIS Factsheet:

De-RISC (Dependable Real-time Infrastructure for Safety-critical Computer) is a European Horizon 2020 Fast Track to Innovation project (Grant Agreement EIC-FTI 869945) that developed a complete space-grade hardware and software platform based on open-source RISC-V architecture.

📅 Project Timeline & Factsheet

Start Date: October 1, 2019
End Date: September 30, 2022
Duration: 36 Months
Funding Scheme: Horizon 2020 (Fast Track to Innovation - GA EIC-FTI 869945)
Grant Agreement ID: 869945
Overall Budget: €3,444,625 (€2,617,937.50 EU Contribution)

🎯 Objectives & Scope

The primary objective of De-RISC was to achieve European technological sovereignty in space computing by delivering a fully European, dependable hardware-software platform for satellite payloads and launcher flight computers, eliminating reliance on non-European proprietary components.

💡 Key Research Innovations

Quad-Core NOEL-V RISC-V Processor SoC: Developed and space-qualified a fault-tolerant quad-core RISC-V multi-core processor SoC.
SafeSU (Safe Statistics Unit): Designed and integrated an on-chip hardware performance counter module to capture multi-core contention and establish tight worst-case execution time (WCET) bounds.
Space Virtualization with Xtratum: Seamlessly integrated space-qualified hypervisor virtualization to host mixed-criticality software partitions with strict spatial and temporal isolation.

🏛️ BSC Key Role & Research Deliverables

As a core research partner in De-RISC, Barcelona Supercomputing Center (BSC) led the microarchitectural safety and timing analysis efforts:

SafeSU Hardware Unit: Conceptualized, designed, and implemented the SafeSU hardware statistics unit for monitoring interconnect contention on NOEL-V platforms.
Multi-Core Interference Characterization: Formulated execution models and timing analysis techniques for evaluating shared-resource contention under space workloads.
Lockstep & Isolation Architectures: Researched lockstep NOEL-V core designs (SafeLS) and hardware execution isolation mechanisms (SafeX).

📚 Associated Publications

G. Cabo, F. Bas, R. Lorenzo, D. Trilla, S. Alcaide, M. Moreto, C. Hernandez, J. Abella — IEEE ETS 2021 ( )
S. Alcaide, G. Cabo, F. Bas, C. Hernandez, J. Abella — IEEE Micro 2023 ( )

🏛️ Consortium Partners

(Partners are listed in no particular order)

The De-RISC consortium brought together leading European space industry, hypervisor, and supercomputing pioneers:

🇪🇸 (Spain, Coordinator)
🇪🇸 (Spain)
🇫🇷 (France)
🇸🇪 (Sweden)

Hardware Design |

NimbleAI

📅 Project Timeline & Factsheet

🎯 Objectives & Scope

💡 Key Research Innovations

🏛️ BSC Key Role & Research Deliverables

📚 Associated Publications

🏛️ Consortium Partners

💼 Industry Advisory Board & Partners

De-RISC

📅 Project Timeline & Factsheet

🎯 Objectives & Scope

💡 Key Research Innovations

🏛️ BSC Key Role & Research Deliverables

📚 Associated Publications

🏛️ Consortium Partners