On-Chip Programmable Traffic Injection for Flexible Cache Coherence Validation

Feb 1, 2026·
F. Fuentes
Dr. Sergi Alcaide Portet
Dr. Sergi Alcaide Portet
,
R. Casanova
,
J. Abella
· 0 min read
Type
Publication
Proceeding of ERTS 2026 on Embedded Real Time Systems
publications
Memory Consistency Cache Coherence Hardware V&V
Authors
F. Fuentes
Dr. Sergi Alcaide Portet
Authors
Dr. Sergi Alcaide Portet (he/him)
Postdoc | Research Engineer
Sergi Alcaide is a PostDoc in the HADES group, within the HPES Lab @ BSC (Barcelona Supercomputing Center)
Authors
R. Casanova
Authors
J. Abella