Application of Tiny RISC-V: Invited paper

Specialized tiny RISC-V cores, typically coupled with scratchpad memories, offer opportunities to manage application-specific units efficiently and autonomously. In general, safety and crypto RISC-V solutions focus too much on big RISC-V cores. In this work, we discuss the standardization of RISC-V architectures based on tiny cores for crypto applications in the context of the PQC4eMRTD project, and then we present key practical contributions from ISOLDE where a tiny RISC-V controller manages a statistics unit (SafeSU) and a traffic injector (SafeTI), both allowing to implement a number of safety and security-related services. The tiny controller builds on scratchpads rather than on cache memories to enhance controllability. Furthermore, a hardware FFT accelerator is coupled to the scratchpad memory developed in ISOLDE, enabling signal processing within the same controlled memory paradigm. This architecture demonstrates a flexible solution for supporting diverse applications, including signal processing, monitoring, and other custom workloads on tiny RISC-V-based systems.