Hardware-Enforced Throughput Quotas for Mitigating Accelerator Interference in Mixed-Criticality SoCs

As open-source Systems-on-Chip (SoCs) scale in complexity, mitigating timing interference across shared resources remains a critical challenge for mixed-criticality applications. This issue is exacerbated by the integration of data-intensive IP cores, whose bursty, high-bandwidth traffic can easily monopolize interconnects and starve latency-sensitive general-purpose processors. While existing open-source Performance Monitor Units (PMUs), such as the original SafeSU architecture, provide cycle-level contention observability, they lack the mechanisms to enforce bandwidth limits natively. This paper presents a significant microarchitectural extension to the SafeSU RTL IP, introducing dynamic, throughput-based quotas. By monitoring data transfer rates over software-configurable time windows, the upgraded hardware actively throttles bandwidth-heavy "noisy neighbor" managers, ensuring strict Quality of Service (QoS) for critical cores. Synthesis and functional evaluations, conducted using the SafeTI programmable traffic injector, demonstrate that the proposed throughput-quota mechanism successfully bounds interconnect saturation while incurring minimal area overhead compared to the baseline SafeSU design.