Publications

Memory Consistency Cache Coherence Hardware V&V

Security Cryptography Standards RISC-V Algorithms Automotive Systems Hardware Memory Program Processors Quantum Cryptography Post Quantum Cryptography Electronic Marchine Readable Travel Documents Embedded Systems Internet Of Things Safety-Critical Systems

Freedom From Interference Mixed-Criticality Systems Performance Monitor Unit Throughput Quotas RISC-V

RISC-V Core Accelerator Safety Security PolyMem Bandwidth

Processor Scheduling Redundancy Road Vehicles GPUs Very Large Scale Integration Software Safety Kernel Standards Nanotechnology

Safety QoS Network On Chip Mixed-Criticality Systems Multicore & MPSoC

AES Encryption Side-Channel Attack Mitigation Multicore & MPSoC Security

Multicore & MPSoC Timing Interference & Validation

RISC-V Robotics

RISC-V Lockstep

RISC-V Lockstep

Computer Architecture Safety-Critical Systems

GPUs Diverse Redundancy Fault Tolerance

GPUs Diverse Redundancy

Programmable Logic Multicore & MPSoC Controllability Observability Safety

Space Applications Multicore & MPSoC Timing Interference & Validation

Diverse Redundancy Safety-Critical Systems

Diverse Redundancy Safety-Critical Systems

RISC-V Safety-Critical Systems QoS

RISC-V Space Applications

GPUs Diverse Redundancy

Multicore & MPSoC Timing Interference & Validation

Lockstep Diverse Redundancy

RISC-V Fault Tolerance Security

Multicore & MPSoC Timing Interference & Validation

GPUs Diverse Redundancy Automotive Systems

Diverse Redundancy Safety-Critical Systems Automotive Systems

GPUs Space Applications

GPUs Diverse Redundancy Automotive Systems

GPUs Safety-Critical Systems Automotive Systems

GPUs Automotive Systems