R. Casanova

Memory Consistency

On-Chip Programmable Traffic Injection for Flexible Cache Coherence Validation

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AES Encryption

On-chip Traffic Injection to Counteract Timing Side-Channel Attacks

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Multicore & MPSoC

SafeTI: A Hardware Traffic Injector for Complex MPSoC Platform Validation and Characterization

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Timing Interference & Validation

SafeTI Traffic Injector Enhancement for Effective Interference Testing in Critical Real-Time Systems

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Timing Interference & Validation

Black-Box IP Validation with the SafeTI Traffic Injector: A Success Story

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