Dr. Sergi Alcaide Portet

Dr. Sergi Alcaide Portet

Postdoc | Research Engineer

Sergi Alcaide is a PostDoc in the HADES group, within the HPES Lab @ BSC (Barcelona Supercomputing Center)

END-TO-END QOS FOR THE OPEN SOURCE SAFETY-RELEVANT RISC-V SELENE PLATFORM (163812675)

p.-andreu

• Jan 1, 2022 • 1 min read

De-RISC: A Complete RISC-V Based Space-Grade Platform (163812676)

n.-wessman

• Jan 1, 2022 • 1 min read

Achieving Diverse Redundancy for GPU Kernels (163812671)

Dr. Sergi Alcaide Portet

• Jan 1, 2022 • 1 min read

SafeTI (108230568): a Hardware Traffic Injector for MPSoC Functional and Timing Validation

o.-sala

• Jun 1, 2021 • 1 min read

SafeDE (108230650): a flexible Diversity Enforcement hardware module for light-lockstepping

f.-bas

• Jun 1, 2021 • 1 min read

Security, Reliability and Test Aspects of the RISC (108230697)-V Ecosystem

j.-abella

• May 1, 2021 • 1 min read

SafeSU (108230728): an Extended Statistics Unit for Multicore Timing Interference

g.-cabo

• May 1, 2021 • 1 min read

GPU (108230665)4S: Major Project Outcomes, Lessons Learnt and Way Forward

l.-kosmidis

• Feb 1, 2021 • 1 min read

GPU4S: Embedded GPUs in space: Latest project updates (163812683)

l.-kosmidis

• Jan 1, 2021 • 1 min read

Software-only triple diverse redundancy on GPUs for autonomous driving platforms (163812685)

Dr. Sergi Alcaide Portet

• Jan 1, 2020 • 1 min read