Sergi Alcaide Portet
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Dr. Sergi Alcaide Portet
☕️
Postdoc | Research Engineer
HPES @ BSC
Sergi Alcaide is a PostDoc in the HADES group, within the HPES Lab @ BSC (Barcelona Supercomputing Center)
Envisioning a Safety Island to Enable HPC Devices in Safety-Critical Domains (163812661)
j.-abella
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Jan 1, 2023
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1 min read
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Black-Box IP Validation with the SafeTI Traffic Injector: A Success Story (163812670)
f.-fuentes
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Jan 1, 2023
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1 min read
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Analysis of Kernel Redundancy for Soft Error Mitigation on Embedded GPUs (163812687)
a.-serrano-cases
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Jan 1, 2023
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1 min read
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A Software-Only Approach to Enable Diverse Redundancy on Intel GPUs for Safety-Related Kernels (163812688)
n.-andriotis
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Jan 1, 2023
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1 min read
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SafeX: Open Source Hardware and Software Components for Safety-Critical Systems (163812679)
Dr. Sergi Alcaide Portet
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Jan 1, 2022
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1 min read
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SafeSU-2: a Safe Statistics Unit for Space MPSoCs (163812678)
g.-cabo
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Jan 1, 2022
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1 min read
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SAFESOFTDR: A LIBRARY TO ENABLE SOFTWARE-BASED DIVERSE REDUNDANCY FOR SAFETY-CRITICAL TASKS (163812674)
f.-mazzocchetti
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Jan 1, 2022
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1 min read
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SafeDX: Standalone Modules Providing Diverse Redundancy for~Safety-Critical Applications (163812666)
r.-canal
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Jan 1, 2022
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1 min read
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SafeDM: a Hardware Diversity Monitor for Redundant Execution on Non-Lockstepped Cores (163812672)
f.-bas
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Jan 1, 2022
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1 min read
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SafeDE: A Low-Cost Hardware Solution to Enforce Diverse Redundancy in Multicores (163812686)
f.-bas
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Jan 1, 2022
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1 min read
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