As open-source Systems-on-Chip (SoCs) scale in complexity, mitigating timing interference across shared resources remains a critical challenge for mixed-criticality applications. …
Specialized tiny RISC-V cores, typically coupled with scratchpad memories, offer opportunities to manage application-specific units efficiently and autonomously. In general, safety …
The SPIDER use case of the ECSEL FRACTAL project demonstrates the safety capabilities developed in the project on a RISC-V platform. The use case demonstrates the integration of a …