J. Abella

Hardware-Enforced Throughput Quotas for Mitigating Accelerator Interference in Mixed-Criticality SoCs

As open-source Systems-on-Chip (SoCs) scale in complexity, mitigating timing interference across shared resources remains a critical challenge for mixed-criticality applications. …

f.-chang

Application of Tiny RISC-V: Invited paper

Specialized tiny RISC-V cores, typically coupled with scratchpad memories, offer opportunities to manage application-specific units efficiently and autonomously. In general, safety …

j.-abella

Enhancing Safety with RISC-V-based SPIDER Autonomous Robot: A Use-Case from the ECSEL FRACTAL Project

The SPIDER use case of the ECSEL FRACTAL project demonstrates the safety capabilities developed in the project on a RISC-V platform. The use case demonstrates the integration of a …

m.-postl

SafeLS: Toward Building a Lockstep NOEL-V Core

m.-sarraseca

Achieving Diverse Redundancy for GPU Kernels

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Dr. Sergi Alcaide Portet