F. Chang

Hardware-Enforced Throughput Quotas for Mitigating Accelerator Interference in Mixed-Criticality SoCs

As open-source Systems-on-Chip (SoCs) scale in complexity, mitigating timing interference across shared resources remains a critical challenge for mixed-criticality applications. …

Enhancing Safety with RISC-V-based SPIDER Autonomous Robot: A Use-Case from the ECSEL FRACTAL Project

The SPIDER use case of the ECSEL FRACTAL project demonstrates the safety capabilities developed in the project on a RISC-V platform. The use case demonstrates the integration of a …

SafeLS: Toward Building a Lockstep NOEL-V Core

SafeLS: An Open Source Implementation of a Lockstep NOEL-V RISC-V Core

SafeX: Open Source Hardware and Software Components for Safety-Critical Systems

Dr. Sergi Alcaide Portet

• Jan 1, 2022 • 1 min read

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SafeSoftDR: A Library to Enable Software-Based Diverse Redundancy for Safety-Critical Tasks

SafeDX: Standalone Modules Providing Diverse Redundancy for~Safety-Critical Applications

End-to-End QoS for the Open Source Safety-Relevant RISC-V SELENE Platform