Dr. Sergi Alcaide Portet ☕️

Dr. Sergi Alcaide Portet

(he/him)

Postdoc | Research Engineer

HPES @ BSC

Professional Summary

Sergi Alcaide is a PostDoc in the HADES group, within the HPES Lab @ BSC (Barcelona Supercomputing Center)
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Education

PhD Computer Architecture

2018-02-13
2023-07-19

UPC (Universitat Politécnica de Catalunya)

MIRI (Master in Innovation abd Research in Information)

2016-01-13
2018-01-25

UPC (Universitat Politécnica de Catalunya)

BS Computer Science

2011-07-18
2015-10-28

UPC (Universitat Politécnica de Catalunya)

Interests

Functional Safety Safety Critical domain Hardware Design RISC-V
Active Research Projects
ISOLDE featured image
Current Project

ISOLDE

High-Performance Open-Source RISC-V Processors & Domain-Specific Accelerators for Critical Applications (Chips JU).

RIGOLETTO featured image
Current Project

RIGOLETTO

Resilient and High-Performance Architecture for Critical Real-Time MPSoCs (Chips JU).

SMARTY featured image
Current Project

SMARTY

Smart and Dependable Architecture for Next-Generation Safety-Critical Systems (Chips JU).

📚 My Research

Use this area to speak to your mission. I’m a research scientist in the Moonshot team at DeepMind. I blog about machine learning, deep learning, and moonshots.

I apply a range of qualitative and quantitative methods to comprehensively investigate the role of science and technology in the economy.

Please reach out to collaborate 😃

Latest Publications
F. Fuentes, Dr. Sergi Alcaide Portet, R. Casanova, J. Abella (2026). On-Chip Programmable Traffic Injection for Flexible Cache Coherence Validation. Proceeding of ERTS 2026 on Embedded Real Time Systems.
URL DOI
J. Abella, Dr. Sergi Alcaide Portet, E. Rufart, L. Kosmidis, A. Puscasu, R. Stancu, O. Buiu, C. Bogdan Ciobanu, C. Vasile, C. Bira (2026). Application of Tiny RISC-V: Invited paper. Proceedings of the 23rd ACM International Conference on Computing Frontiers: Workshops and Special Sessions.
URL DOI
F. Chang, O. Alymlahi, F. Fuentes, E. Rufart, Dr. Sergi Alcaide Portet, J. Abella (2026). Hardware-Enforced Throughput Quotas for Mitigating Accelerator Interference in Mixed-Criticality SoCs. Proceedings of the 23rd ACM International Conference on Computing Frontiers: Workshops and Special Sessions.
URL DOI
L. Kosmidis, Dr. Sergi Alcaide Portet, M. Maria Trompouki, A. Escobar-Molero, A. Anglart, D. Van Geest, M. Zuber, J. Truong, A. Grebenc, D. Houdeau (2026). Introduction to Post Quantum Cryptography for Resource Constrained Systems. 2026 IEEE European Test Symposium (ETS).
DOI
P. Andreu, Dr. Sergi Alcaide Portet, P. Lopez, J. Abella, C. Hernandez (2025). Expanding SafeSU capabilities by leveraging security frameworks for contention monitoring in complex SoCs. Future Generation Computer Systems.
URL DOI
See all

Education

PhD Computer Architecture

UPC (Universitat Politécnica de Catalunya)

Hardware/software solutions to enable the use of high-performance processors in the most stringent safety-critical systems
Download dissertation

MIRI (Master in Innovation abd Research in Information)

UPC (Universitat Politécnica de Catalunya)

Download dissertation

BS Computer Science

UPC (Universitat Politécnica de Catalunya)

Languages
100%
Catalan Native
100%
Spanish Native
80%
English Fluent